TSMC CoWoS Yield Tops 98% for Some Lines, Targets 14x Reticle Size by 2029

TradingKey - On August 11, TSMC disclosed at the OCP APAC Summit that its 5.5x reticle size CoWoS advanced packaging solution has entered the volume production stage. The solution can accommodate up to 12 HBM4 stacks and has been validated across products of multiple AI customers, with yields for certain AI chips consistently exceeding 98%, and individual cases even reaching 99%.

Following the news of the CoWoS yield breakthrough, TSMC's stock price extended its gains. In US stock trading on August 12, TSMC's ADR (TSM) closed at $429.15, up 1.68% from the previous trading day, touching an intraday high of $433.28.

[Source: TradingView]

Jun He, Vice President of Advanced Packaging Technology and Service at TSMC, stated that over the past three years, the company's CoWoS capacity has expanded at a rate that almost doubled every year, and TSMC currently operates 10 advanced packaging facilities. Institutional investors estimate that TSMC's monthly CoWoS capacity is expected to reach 140,000 wafers by the end of 2026 and further increase to 220,000 wafers in 2027.

In addition to expanding capacity, TSMC is also continuing to advance larger-size advanced packaging. He revealed that the company aims to further increase the package size to 14x reticle specifications by 2029, at which time a single package will be able to accommodate up to 10 large compute dies and 20 HBM stacks.

However, as package sizes continue to expand, manufacturing difficulty rises correspondingly. As logic chips, HBM, interposers, and substrates are integrated into larger packages, thermal expansion differences between different materials, mechanical stress, and thermal dissipation issues become even more prominent. The larger the package scale, the more likely any localized defect could impact the stable operation of the entire AI system.

He therefore pointed out that for high-density AI data centers, relying solely on individual components to meet high reliability standards is no longer sufficient. To keep the overall failure rate within an acceptable range, the reliability of certain package components even needs to exceed automotive-grade standards. This also means that competition in next-generation AI chips is no longer limited to process nodes alone, but is gradually shifting toward collaborative optimization across chips, HBM, advanced packaging, thermal dissipation, and systems.