SK Hynix Unveils CPO Roadmap: Optical Interconnect Technology Extends to Memory Interfaces for the First Time

TradingKey - On August 20, 2026, SK Hynix (SKHY), in collaboration with multiple institutions including the University of Virginia and Massachusetts Institute of Technology, published a paper in the top international journal Nature Electronics, systematically disclosing its Co-Packaged Optics (CPO) technology roadmap for the first time.

Driven by the dual positive catalysts of the CPO roadmap disclosure and a 40 trillion KRW (approximately $28.6 billion) buyback plan, SK Hynix's South Korean shares closed up 12.73% for the day at 1.691 million KRW.

[Source: SKhynix]

[Source: TradingView]

The paper points out that as AI clusters expand from single chips to ultra-large-scale clusters composed of thousands of GPUs and HBMs, data transmission between racks is becoming a new constraint.

Data shows that computing power grows by roughly three times every two years, while interconnect bandwidth increases by only about 1.4 times over the same period. This widening gap forms a "bandwidth wall" bottleneck. The paper positions CPO as a critical path to breaking through this bottleneck.

The paper further proposes an "optics-centric" long-term architectural vision. The unique aspect of this vision is that while current CPO primarily addresses optical interconnects between processors and racks, SK Hynix aims to extend optical interconnects to the memory interface.

By directly connecting processor resource pools and memory resource pools through photonic interposers, multiple AI accelerators can share the same large-capacity memory pool, breaking through existing physical packaging limitations.

The research team also set specific technical specifications for next-generation AI infrastructure: single-node bandwidth exceeding 100 Tb/s, energy consumption below 1 pJ/bit, and chip-to-chip latency below 10 nanoseconds.

The paper also outlines the evolutionary path from 2D packaging to 2.5D interposers and then to 3D heterogeneous integration, listing key technical challenges that must be overcome for commercialization.

Seung-Hoon Hong, head of SK Hynix's AI Infrastructure Team, stated that memory companies are evolving from providing single components to becoming partners that help customers enhance overall system competitiveness through technologies such as CPO.

Kyusang Lee, a professor at the University of Virginia, stated directly that no matter how powerful computing chips are, if data transmission between chips cannot keep up, overall system performance cannot improve, making the replacement of copper interconnects—which face inherent physical limitations—with optical interconnects an inevitable path; the core of the entire research is an "optics-centric" co-design that treats memory devices, controllers, optical devices, and packaging as a unified system.