QuickLogic (QUIK) Q4 2025 Earnings Call Transcript

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DATE

Tuesday, March 3, 2026 at 5:30 p.m. ET

CALL PARTICIPANTS

• President and Chief Executive Officer — Brian Faith
• Senior Vice President and Chief Financial Officer — Elias Nader
• Investor Relations, Darrow — Alison Ziegler

TAKEAWAYS

• Total Revenue -- $3.7 million, representing a decrease of 35% year over year and an increase of 84% quarter over quarter from Q3 2025.
• New Product Revenue -- $2.8 million, down 39% year over year, up 199% from Q3 2025.
• Mature Product Revenue -- $900,000 for the quarter, down from $1 million a year prior, and down from $1.1 million in Q3 2025.
• Non-GAAP Gross Margin -- 20.8%, affected by $473,000 in inventory reserves and $135,000 in unexpected professional services costs in cost of goods sold.
• Non-GAAP Operating Expenses -- $3.5 million, $500,000 above the forecast midpoint due to executive incentives recognized in Q4.
• Non-GAAP Net Loss -- $2.9 million, or $0.17 per share, compared to a $600,000 profit ($0.04 per share) in Q4 2024, and a $3.2 million loss ($0.19 per share) in Q3 2025.
• Stock-Based Compensation Expense -- $700,000, versus $900,000 in Q4 2024 and $800,000 in Q3 2025.
• Cash Balance -- $18.8 million at quarter end (including $15 million drawn on the credit facility), compared to $17.3 million in Q3 2025 (also including $15 million on the facility).
• ATM Equity Raise -- $3.2 million raised during Q4, contributing to the $1.5 million net cash increase in the quarter.
• Three Major Customers -- Three customers each accounted for 10% or more of Q4 revenue.
• U.S. Government Contract Tranche -- Awarded $13 million in new funding, with revenue to begin recognition in Q1 2026; total contract ceiling now $89 million.
• Q1 2026 Revenue Guidance -- $5.5 million plus or minus 10%, including $4.5 million from new products and $1 million from mature products.
• Q1 2026 Non-GAAP Gross Margin Guidance -- Approximately 45% plus or minus 5%, with a full-year forecast of 57% non-GAAP gross margin.
• Q1 2026 Non-GAAP Operating Expenses Guidance -- Approximately $3.2 million plus or minus 5%.
• Full-Year 2026 Non-GAAP OpEx Guidance -- $13.5 million, reflecting a 14% increase to support revenue growth expectations.
• Q1 2026 Net Loss Guidance -- Expected loss of about $800,000, or $0.04 per share.
• Additional Q1 2026 ATM Raise -- $3.2 million raised early in Q1.
• Q1 2026 Projected Cash Use -- Net projected cash use of $1.4 million, negatively impacted by government contract payment timing.
• Impairment Charge -- Large non-cash impairment charge was taken on SensiML due to it being held for sale for over a year.
• SRH FPGA Test Chip Progress -- Self-funded SRH FPGA test chip samples received; initial dev kit orders announced as of January 14.
• Multi-Project Wafer (MPW) Tape-outs -- Three MPW tape-outs planned for 2026 related to the storefront program; two tape-outs fully contracted, and a third potentially partially funded by contracts.
• Architectural Enhancements -- Enhancements delivered for the $1 million lead feasibility study can be applied to all advanced nodes (12nm and below), improving power, performance, and area (PPA).
• Intel 18A Contracts -- Three smaller contracts total "well over $1 million," with a potential fourth contract pending, bringing the total to nearly $2 million.
• Epson Case Study -- QuickLogic Corporation's eFPGA hard IP enabled 50% power reduction in Epson's SoC, validated for TSMC E12N process integration.
• Storefront Model -- Management forecasts the storefront business model to contribute meaningful revenue starting in 2026, driven by SRH FPGA offerings and related IP sales.

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RISKS

• Non-GAAP gross margin in Q4 was reduced due to $473,000 in inventory reserves and $135,000 in unanticipated contracted professional services costs recognized in cost of goods sold.
• Elias Nader said, "there are several factors that we believe will weigh on our non-GAAP gross profit margin during 2026," citing high services revenue mix, costs for leased software tools, and use of outside engineering services that are largely modeled as cost of goods sold in the first half.
• Large non-cash impairment charge was recognized for SensiML after more than a year as an asset held for sale, with no current assurance of a divestiture transaction.
• Timing of significant contract awards, especially with government or commercial customers, remains uncertain and could result in revenue lumpiness and delayed recognition.

SUMMARY

QuickLogic Corporation (NASDAQ:QUIK) reported a sharp year-over-year revenue decline and negative non-GAAP net results, but management communicated an expected recovery through significant Q1 sequential growth and a robust pipeline. The $13 million U.S. government contract tranche, combined with orders for the SRH FPGA dev kit, launch the company's expanded government and defense engagement, with initial revenue recognition starting in Q1. Management forecasts multi-project wafer tape-outs will drive the storefront model, supported by both defense and non-defense commercial commitments. The company detailed architectural enhancements enabling addressable markets at advanced process nodes, positioning QuickLogic Corporation for upcoming awards by integrating its eFPGA hard IP into leading-edge ASIC and chiplet designs, with revenue opportunities tied to both ongoing evaluations and future contract wins. Cost headwinds related to inventory reserves, unplanned engineering costs, and a substantial SensiML impairment are expected to impact margins in the near term, but Q1 is forecast to be the low point for 2026 with sequential growth anticipated for the rest of the year, potentially producing 50%-100% revenue growth for the full year.

• Faith said, "So we actually think that Q1 is going to be the low point for the year. Right? We will give that breadcrumb that the other quarters will be over Q1," specifying anticipated sequential growth and acknowledging possible revenue lumpiness as contract timing remains an uncertainty.
• Nader indicated, "we are expecting cash flow positive in the second half of the year for sure, not the first half." He also expects net income to become positive only in the second half as revenue ramps.
• Faith said that among highest-radiation "major programs" targeted, total "socket opportunities" are "10 to 20," with less than five major programs currently in focus; these near-term dev kit orders target the most highly differentiated defense applications.
• Management confirmed three planned MPW tape-outs are all for process nodes already supported, with end customers driving development and two tape-outs fully funded, mitigating capital risk.
• Faith emphasized QuickLogic Corporation is presently "the only source available today for a U.S.-fabricated FPGA that addresses the full spectrum of radiation hardness requirements," highlighting a unique competitive position in strategic defense.
• The quarter saw major progress integrating QuickLogic Corporation's eFPGA hard IP with both defense and non-defense customers, including a high-profile commercial win for a 12nm data center peripheral chip and a case study with Epson yielding meaningful power savings.
• Management stressed that full-year growth is highly dependent on the timing and scope of additional IP contracts and the pace of both government and commercial customer evaluations.

INDUSTRY GLOSSARY

• DIB: Defense Industrial Base; refers to U.S. companies supplying products or services to defense and national security programs.
• SRH FPGA: Strategic Radiation Hard Field Programmable Gate Array; a U.S.-fabricated device specifically engineered to meet stringent radiation resistance requirements demanded by defense and space applications.
• Storefront Model: QuickLogic Corporation's commercial model in which off-the-shelf products or IP are offered to multiple customers for rapid acquisition, as opposed to custom-designed solutions.
• MPW (Multi-Project Wafer) Tape-out: A manufacturing approach that allows multiple chip designs to share a single production wafer for reduced costs and quicker prototyping, used as a key step before final productization.
• eFPGA Hard IP: Embedded Field Programmable Gate Array intellectual property delivered as hardened (fully-synthesized, silicon-proven) blocks for direct integration into customer ASICs.
• PPA: Power, Performance, and Area; critical metrics in semiconductor design that measure efficiency, processing speed, and chip real estate usage, respectively.

Full Conference Call Transcript

Operator: Ladies and gentlemen, good afternoon. At this time, I would like to welcome everybody to QuickLogic Corporation's fourth quarter and fiscal 2025 earnings results conference call. As a reminder, today's call is being recorded. I would now like to turn the conference over to Ms. Alison Ziegler of Darrow. Ms. Ziegler, please go ahead.

Alison Ziegler: Thank you, operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic Corporation makes today are forward-looking statements that involve risks and uncertainties, including, but not limited to, statements regarding our future profitability and cash flows, expectations regarding our future business and expected revenue growth, and statements regarding the timing, milestones, and payments related to our government contracts.

Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risks that new orders may not result in future revenues, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low power, competitive pricing, and short time to market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters, and other business interruptions that could disrupt supply or delivery of or demand for the company's products, and changes in tax rates and exposure to additional tax liabilities.

For more detailed discussions of the risks, uncertainties, and assumptions that could result in those differences, please refer to the risk factors discussed in QuickLogic Corporation's most recently filed periodic reports with the SEC. QuickLogic Corporation assumes no obligation to update any forward-looking statements or information, which speak as of the respective dates, of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR webpage that provides current and historical non-GAAP data.

Please note QuickLogic Corporation uses its website, the company blog, corporate X account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information. QuickLogic Corporation may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic Corporation's IR webpage shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.

Brian Faith: Thank you, Alison. Good afternoon, everyone, thank you all for joining our fourth quarter 2025 conference call. While certain contract delays over the course of the year resulted in much lower than expected 2025 revenue, we accomplished numerous tangible milestones that set the stage well for 2026 and beyond. Underscoring this is our forecast for nearly 50% sequential revenue growth in Q1, large contracts for very high-density eFPGA hard IP cores that are in late stages of negotiation, and the acceleration of our storefront business model, which we believe will drive a meaningful revenue contribution beginning in 2026. I will take a few minutes now to update you on these and other accomplishments.

In our February 18 press release, we announced QuickLogic Corporation was awarded a $13 million tranche for our ongoing contract with the U.S. government that was initiated in 2022. We will begin recognizing revenue from this tranche in Q1. In line with my comments during our last earnings conference call, this tranche funds increased quarterly revenue recognition relative to 2025. In parallel with our U.S. government contract, QuickLogic Corporation internally funded the development of an SRH FPGA test chip. Last August, we delivered design files to GlobalFoundries to fabricate our SRH FPGA test chip using its 12LP process.

This chip was designed to meet the specific requirements of certain large DIBs that have programs in development today that are good candidates for this device. This investment positions us very well as the only source available today for a U.S.-fabricated FPGA that addresses the full spectrum of radiation hardness requirements. We received our SRH FPGA test chip samples earlier in Q1 and announced in a January 14 press release that we have received orders for our SRH FPGA dev kit that enables DIBs to evaluate the test chips.

I view this as a strong demand signal and our first tangible step towards what I believe will be hundreds of millions of dollars in potential storefront business for our discrete SRH FPGA during coming years. Beyond the discrete SRH FPGA market, we are leveraging this test chip to cast a much broader net. In addition to the applications that require strategic radiation hardness that are most likely to design using our storefront discrete SRH FPGA, there are many other applications with less rigorous radiation requirements that may prefer to integrate our SRH eFPGA hard IP in ASICs. DIBs are already using GlobalFoundries' 12OP fabrication process for various levels of radiation hardness in ASIC designs.

By demonstrating our SRH FPGA test chip that is also fabricated on 12OP, we are positioning QuickLogic Corporation to address both discrete SRH FPGA requirements as well as provide DIBs with the confidence they need to integrate our SRH eFPGA hard IP in future ASIC designs. In some cases, these DIBs may also elect to utilize our storefront services for their ASIC designs. The short story here is by leveraging the milestones accomplished in 2025, we believe we are very well positioned to successfully address both discrete and embedded FPGA designs across the full spectrum of radiation hardness requirements.

And with the architectural enhancements we implemented last year that are extensible to 12OP, we have significantly expanded our SAM in these markets to include the lucrative applications for very high-density discrete and embedded FPGA. During our last conference call, I stated that a mid 7-figure eFPGA hard IP contract leveraging Intel 18A was pushed into 2026 due to a delay in government funding. Based on our conversations with this DIB, we remain highly confident we will be awarded this contract once it is funded. While the timing of funding remains uncertain, our discussions with this DIB have expanded to include the potential of QuickLogic Corporation providing storefront services for the customer-designed ASIC that includes our eFPGA hard IP.

We expect that we will learn more about the potential expansion to storefront and the timing for this award in the coming months. During this funding delay and the discussions about expanding the scope of our participation, we have worked closely with this DIB on a variety of projects. Through these efforts, we have been awarded three smaller Intel 18A contracts that total well over $1 million and a fourth is pending that will bring the total to nearly $2 million. The first two contracts were for Intel 18A test chips. We delivered IP for both in 2025 and expect to receive an allotment of test chips for our internal evaluation next quarter.

The third contract was for a $1 million lead feasibility study that we completed in Q4. A fourth contract, which we anticipate being awarded yet this quarter, leverages the architectural enhancements developed during the $1 million lead study. In support of this contract, we will deliver hard IP for a very large Intel 18A eFPGA core the customer plans to integrate into its ASIC that is targeted for tape-out during 2026. The architectural enhancements we developed in support of the $1 million lead study can be leveraged across all advanced fabrication nodes, which we define as 12 nanometers and smaller.

These enhancements reduce power consumption, increase performance, and reduce the silicon area required for a given size block of our core FPGA technology. In industry terms, the enhancements materially improve our PPA. With these architectural enhancements in place, we can address the lucrative markets that require very high-density eFPGA cores in ASIC designs and very high-density discrete FPGAs. This significantly expands our SAM for eFPGA hard IP and discrete devices including our SRH FPGA, chiplets, and other storefront opportunities. In addition to these DIB contracts, we are working closely with a large commercial customer on a new Intel 18A contract valued at several million dollars. We originally expected this contract would be awarded in late Q4.

However, the customer decided to expand the size of the eFPGA core in their ASIC to provide greater programmable flexibility. While this is a beneficial trend for QuickLogic Corporation, it has delayed the contract award. We are currently forecasting this contract will be awarded during Q2. During our November 2025 conference call, I stated that we would soon announce the expansion of our involvement with a DIB that specializes in cybersecurity for strategic and tactical weapon systems. On December 8, we issued a press release announcing Idaho Scientific selected our eFPGA hard IP for forward-leaning hardware-based cryptographic solutions designed to address mobile IoT infrastructure and defense systems.

Idaho Scientific has a rich history of leveraging FPGA technology to deliver robust security systems that can adapt quickly to changing external threats without the vulnerabilities that are inherent in software-based solutions. By integrating our eFPGA hard IP into its secure system-on-chip processors, it can further enhance its cryptographic security and address new markets much more quickly and with lower risks and lower costs. Last April, we announced an eFPGA hard IP contract with a new defense industrial base customer valued at $1.1 million that will be fabricated on the GF-12OP process. This application utilizes a large block of our eFPGA hard IP critical functions, which is a trend we are seeing in designs targeting advanced fabrication nodes.

With the cooperation of this DIB and its end customer, we are leveraging the large eFPGA core into a new 7-figure contract that we expect to announce this year. However, due to the fact this contract involves multiple parties, it is taking longer than we expected to finalize. Based on current forecast, we anticipate the contract award later this quarter. In the scope of this new contract, we will be provided with test chips that we will incorporate in an evaluation. The evaluation kit, which is currently scheduled for late 2026, will be compatible with common third-party development environments used by both DIBs and commercial customers.

This enables these customers to accelerate system-level evaluations and designs that can use either a storefront version of the discrete FPGA or our eFPGA hard IP in an ASIC. In parallel with these efforts, we are exploring the potential to leverage the FPGA as a chiplet that is co-packaged with one of our partners' microcontrollers. We are already seeing interest from some of our partners on this concept. We completed the initial phase of our digital proof-of-concept chiplet program in 2025 as a strategy to accelerate our storefront chiplet initiative. Internally, we refer to this as POC.

With the support of our large strategic partners, we leveraged our existing eFPGA hard IP and readily available third-party IP to move this program forward rapidly and with minimal investment. With ongoing debates regarding the communications and protocol layers of chiplet interfaces, this POC and our decades of experience in FPGA bridging positions us well as a potential solution to move chiplet designs forward to satisfy what appears to be significant pent-up demand. We were invited to present a paper on our POC at the recent Chiplet Summit and at the Intel Foundry's Partners presentation at the upcoming GOMAC, together with Cadence and Trusted Semiconductor Solutions.

The net takeaway from our presentation at the Chiplet Summit supports our optimism that chiplets will build traction in 2026. The primary hurdles today are interoperability gaps, and we believe a storefront FPGA chiplet is the logical solution for a programmable bridge. Earlier this year, Epson gave us permission to share its case study that supports our claims that using FPGA technology to process algorithms lowers power consumption without sacrificing programmability relative to processing in software. We published the results in a blog post on January 13. Epson's SoC was originally architected to run workloads entirely in software, but as demand for more features and real-time responsiveness grew, power consumption became a limiting factor.

Epson's engineering team recognized that moving compute-intensive functions into dedicated hardware could deliver significant efficiency gains. But the hardware solution would need to be capable of adapting to changes in algorithms. This meant the only practical solution would be an eFPGA core integrated inside the SoC. By using our proprietary Australis eFPGA IP generator, we were able to quickly deliver a customized hard IP core specifically designed to the SoC application that targeted TSMC's E12N fabrication technology. Adding to our challenge was the fact that this would be our first eFPGA hard IP for E12N. From design handoff to silicon validation, the IP integrated cleanly into Epson's SoC without the need for re-spins or late-stage design changes.

Epson was able to boot, configure, and validate the eFPGA subsystem immediately, accelerating its schedule and reducing risk. After final testing, Epson confirmed the resulting design reduced overall power consumption by 50%. This makes a huge difference for battery-powered systems. Given our success in this design, we believe we are very well positioned for future opportunities with Epson as well as other companies with similar requirements. As I am sure you noticed in our 8-K, we took a large impairment charge on SensiML. This is due to the standard accounting practice to impair the value of an asset held for sale for a year or longer.

During the last year, we have discussed the divestiture of SensiML with microcontroller companies and in one case, those discussions advanced to due diligence but were concluded without an agreement. We are in discussions today with a large company where SensiML software potentially presents high value for new AI and drone projects. We cannot provide assurance that this or other discussions will result in a transaction. With that, I will turn the call over to Elias for his presentation of financial data.

Elias Nader: Thank you, Brian. And good afternoon, everyone. Total fourth quarter revenue was $3.7 million. This was down 35% from Q4 2024 and up 84% from Q3 2025. New product revenue in Q4 was $2.8 million and mature product revenue was $900,000. New product revenue was down 39% from Q4 2024, and up 199% compared to Q3 2025. Mature product revenue was down from $1 million in 2024 and $1.1 million in 2025. Non-GAAP gross margin in Q4 was 20.8%. The primary reasons the non-GAAP gross profit margin was below my outlook are $473,000 in inventory reserves and $135,000 in contracted professional services costs attributable to COGS that were not anticipated at the time of our last conference call.

The balance is mostly attributable to a higher than expected contribution from professional services relative to IP and mature product revenue. Non-GAAP operating expenses in Q4 were approximately $3.5 million. This was $500,000 above the midpoint of our outlook due to the booking of certain executive incentives in Q4. This compares with non-GAAP operating expenses of $2.9 million in 2024 and $2.9 million in 2025. Non-GAAP net loss was $2.9 million or $0.17 per share. This compares to a non-GAAP net income of $600,000 or $0.04 per diluted share in Q4 2024, and a non-GAAP net loss of $3.2 million or $0.19 per share in 2025.

The difference between our GAAP and non-GAAP results is related to non-cash stock-based compensation expenses and the non-cash impairment charge for SensiML that Brian mentioned. Stock-based compensation for Q4 was $700,000 compared to $900,000 in Q4 2024 and $800,000 in Q3 2025. For the fourth quarter, three customers accounted for 10% or more of total revenue. At the close of Q4, total cash was $18.8 million, inclusive of $15 million from our credit facility. This compares with $17.3 million inclusive of $15 million from our credit facility at the close of Q3 2025. This increase of $1.5 million in net cash is inclusive of $3.2 million raised with our ATM during Q4.

Now moving to our guidance and outlook for our fiscal first quarter, which will end on March 29, 2026. Based on backlog and customer forecast, our total revenue guidance for Q1 is $5.5 million plus or minus 10%. We expect total revenue to be comprised of $4.5 million in new product revenue and $1 million in mature product revenue. For the full year, we anticipate product revenue will be approximately $4 million. Based on the anticipated Q1 revenue mix, non-GAAP gross margin for the first quarter is expected to be approximately 45% plus or minus 5%. For the full year 2026, we are modeling a 57% non-GAAP gross profit margin.

However, there are several factors that we believe will weigh on our non-GAAP gross profit margin during 2026. We are modeling services revenue will be a high percentage of total revenue during the first half. In support of services, we will have costs for software tools that we lease and we will utilize outside engineering services in addition to our internal resources. A large percentage of these costs are currently being modeled as COGS. We expect some percentage of these costs will be capitalized, but it is unclear at this point the exact percentage.

Also, during the first half, we will incur certain significant costs associated with large contracts that will be recognized late during the quarter, and the offsetting revenue will not be recognized until the following quarter. We are modeling these factors as negatively impacting our non-GAAP gross profit margin during Q1 and Q2. Among the significant costs we are modeling for fiscal 2026 are three multi-project wafer, or MPW, tape-outs. All three tape-outs are for products that we intend to sell via our storefront program. The costs associated with two of these tape-outs will be fully covered by customer contracts. One of these contracts is already on the books and another is in the very late stages of negotiation.

We believe the cost associated with the third tape-out will be covered at least in part by contracts. If contracts are secured in advance of this tape-out, it would be an upside to our full-year model. Please note that given the nature of our industry, we may occasionally need to assign certain expenses to COGS versus OpEx or capitalize certain costs. These classifications are related to labor and tooling for IP products—IP contracts, pardon me. This may cause variability in our quarterly gross margins and operating results that will usually balance out on the operating line. With that in mind, our Q1 non-GAAP operating expenses are expected to be approximately $3.2 million plus or minus 5%.

We are expecting full-year non-GAAP operating expenses to be $13.5 million. This forecasted growth of 14% in non-GAAP OpEx over 2025 is to support our anticipated revenue growth in 2026. After interest and other income, we are forecasting a Q1 net loss of about $800,000 or a loss of approximately $0.04 per share. The main difference between our GAAP and non-GAAP results is related to non-cash stock-based compensation expenses. In Q1, we expect this compensation will be approximately $800,000, which is similar to Q4 2025 and Q1 2025. As a reminder, there will be movements in our stock-based compensation during the year, and it may vary quarter to quarter based on the timing of grants.

Prior to this conference call, we raised approximately $3.2 million during Q1 using our existing ATM. We anticipate Q1 cash use, net of money raised with our ATM, will be approximately $1.4 million. Our projected Q1 cash use is negatively impacted by the expected timing of payments attributable to our prime U.S. government contract. The timing of these payments during the year is expected to benefit cash flow during the second half. As a heads up, we are working to secure a new banking partner as we are focused on obtaining more favorable terms that will lower our costs and purposely reduce our line of credit from $20 million to $10 million. Thank you for your time.

And with that, I will now turn the call over to Brian for his closing comments.

Brian Faith: Thank you, Elias. Through hard work, dedication, and long hours, the QuickLogic Corporation team accomplished numerous strategic milestones in 2025 that have enabled us to enter 2026 on extremely sound footing. Thank you all for what you have accomplished. Our continued performance in our prime U.S. government contract has led to its expansion to a potential $89 million, the addition of GlobalFoundries and its 12OP fabrication process which is used today by numerous DIBs for a variety of radiation hardness requirements, and most recently, the award of a $13 million tranche. Independent of this contract, QuickLogic Corporation funded its own strategic radiation hard, or SRH, discrete FPGA test chip.

We now have test chips in hand as well as orders for SRH FPGA dev kits that will enable DIBs to evaluate our test chip for the full spectrum radiation hardness requirements. This significantly accelerates our ability to win both discrete SRH FPGA designs we can storefront as well as designs that are better suited to embed our SRH eFPGA hard IP in ASICs. To further accelerate our storefront business model in 2026, we are planning three multi-project wafer, or MPW, tape-outs this year. All three tape-outs are for chips that we intend to sell via our storefront program.

The cost for two of these tape-outs will be fully covered by customer contracts, one of these contracts is already on the books and another is in the very late stages of negotiation. We believe the third tape-out will be covered at least in part by contracts. Through a revenue-generating contract with a customer, we developed architectural enhancements for our core eFPGA technology that enable us to address the lucrative markets for very high density, both discrete and embedded designs. These enhancements were initially developed for Intel 18A and are extensible to all advanced fabrication nodes.

Given the sound foundation of the recently awarded U.S. government contract, our outlook for continuing mature business of approximately $4 million in 2026, and the number of pending contracts that are in the late stages of negotiation, we believe we are well positioned to deliver between 50–100% revenue growth in 2026.

Elias Nader: With that—

Brian Faith: I will turn the call over for questions.

Operator: Thank you. You may press 2 if you would like to remove your question from the queue. And for participants using speaker equipment, it may be necessary to pick up your handset before pressing the star keys. Our first question is from Richard Shannon with Craig-Hallum Capital Group. Please proceed.

Richard Cutts Shannon: Thanks, Brian and Elias, for taking my questions.

Brian Faith: Hey, Richard. Hey.

Richard Cutts Shannon: Brian, you kind of saved the best for last here with the outlook for the year here. So, I guess, I will start with that topic here and ask for a little bit of help in trying to think about the dollar growth here contributions as we go from ’25 to ’26 in that 50 to 100% here. I wonder if you could portray that by storefront contribution, defense versus commercial, and any other ways you would like to split that up, please?

Brian Faith: Sure. So as I said, $4 million of that is going to be our base mature business, which we are very comfortable with at this point for the year. And then, of course, the $13 million tranche for the U.S. government contract. So that is $17 million. If you were to look at the range of 50 to 100%, obviously we need to get well into the 20s to get to that. And we are expecting that there will be additional contracts that are defense related for either one of those MPW test chips that I alluded to and/or IP that would be to defense contractors for use in their ASICs.

As I mentioned, as we have gone and upgraded our architecture to support higher LUT counts, we are seeing a lot of interest in that type of architecture for some of these process technologies that are tried and true for U.S. defense companies like 18A and 12OP. And then if you go on top of that a little bit further, we see other commercial IP opportunities, of which I mentioned during the call that we felt was pushed into 2026 from 2025 with that commercial customer specifically because they were looking at making the IP core larger to handle more capability.

And so there were a lot of architectural discussions and trade-offs going on that sort of naturally pushed that IP contract into what we are now forecasting to be 2026. But that would be a non-defense customer for that particular IP license. Does that help give color to the question, Richard?

Richard Cutts Shannon: Yes, it does here. So maybe I would—I probably should have asked this as a multiple-part question here, but maybe just want to get a little sense of what are the differences between high and low end of that range here. I think I heard part of it, but I would love to hear you put that all together, please.

Brian Faith: Sure. So if you look at the low end of that range, that would definitely be the base $4 million business, the current tranche that we have for the government contract, and I would say a couple of IP licenses, one of which would be useful for one of these MPW tape-outs. And then the higher end, or even exceeding the higher end of that, would be as we layer additional IP licenses on top of that, and perhaps even further funding on the government contract.

Elias Nader: Okay.

Richard Cutts Shannon: That is helpful. Maybe a couple other questions for me here. So big picture, when we look at strategic RadHard, both—I ask this question both as FPGAs as well as the opportunity to storefronts for ASICs to include your IP here. What do we think, or how do we think about timing of wins with any of these DIBs for, you know, I think, substantial programs? I think that was the intention of this program all along here. Help us understand what you are expecting to happen this year versus in the following years.

Brian Faith: So this year, we are expecting evaluations to take place using our test chips, either ours or the government-funded one, and then getting to some sort of architecture understanding with these DIBs by the end of this year, this fiscal year. Next year, actual development activity with those chips. So to be clear, this year is very much an evaluation year. All of these companies are very risk averse from a technical perspective, and so they need the time to dig into the test chip and make sure that they understand it and are comfortable with the tools that go along with it, meaning our software tools, and the device and the dev kits themselves.

So, meaning exiting this year with their positive feedback and sort of thumbs up that they want to move forward with architecture insertion the next year.

Richard Cutts Shannon: Okay. That is helpful perspective. Maybe jumping back quickly to thought process for the year here, you mentioned a sales number and then Elias also gave us some other numbers. I was not able to put those together here to understand whether we are going to be net income positive or cash flow positive here. Maybe you can help us understand your thought process either, both at the low and the high end of your sales guidance range.

Elias Nader: Well, I will tell you, we are expecting cash flow positive in the second half of the year for sure, not the first half, Richard.

Richard Cutts Shannon: Okay. And how about net income? Or EPS? What is that looking like from the top to bottom line?

Elias Nader: Same. I think we will be on the high end in the second half of the year and not the first half as well. But I expect to be both positive on net income in the second half of the year.

Richard Cutts Shannon: Okay. That is helpful. And one last question for me, and I will jump on the line here. Brian, you mentioned targeting three MPWs this year, and I think I have lost a couple of it or some of the details you offered regarding that. But maybe help us understand the dynamics here and is this something that is kind of follow-on to the ones you got on last year or are these blossoming opportunities that you expect to continue to do here? Like how should we think about these? And I cannot remember also, did you mention the process node or even foundries of those? Yeah. Thank you.

Brian Faith: Yeah. We did not mention process technology for these, and I am not going to. But they are based on process technologies that we already support, so we do not have to do an actual physical port to a new process to execute on these. And I think we are trying to convey that two of these will be fully covered by customer contracts, and one of them would be partially covered by the contract. The key here being that there are going to be end customers associated with all three of them.

They are the driving force behind the definition of these and, in some cases, like we mentioned, either partially or fully funding the development of them during the year.

Richard Cutts Shannon: Okay. Sounds good. I will jump on the line, guys. Thank you.

Brian Faith: Thanks, Richard.

Operator: Our next question is from Neil Young with Needham & Company. Please proceed.

Neil Young: Hey, everyone. Thank you for letting me ask some questions.

Brian Faith: Hey, Neil.

Neil Young: The first question, I wanted to ask about the high performance data center win that you talked about in the press release. Maybe if you could dig a little bit deeper in that, you know, share what the application is, you know, just any other color I think would be interesting. Thanks.

Brian Faith: Sure. So this is a 12-nanometer design and it is for an eFPGA IP core. The eFPGA IP core for this particular one is a meaningful percent of the die size, meaning it is not just an insurance policy. It is actually delivering capability that they have architected in from day one to be very important for the functionality of this chip. Because it is not a 3- or 4-nanometer chip, obviously it is not going to be a GPU-class device. But there are a lot of peripheral components in these data center printed circuit boards that surround those types of devices.

And this would be an example of one of those, let us call it peripheral chips, that are still important and critical for overall functionality but not the core of the compute. So we are continuing to execute on that, continuing our engagement with the customer, and hopefully supporting their tape-out at some point later this year. You know, now that I think about it, I am glad you brought it up, Neil, because this is sort of probably the largest IP contract we have had in recent times for a non-defense application. And a lot of people have asked us, repeatedly, are you going to be beyond just defense? And we said yes.

And I think we are glad that we are able to talk about this particular example because it clearly is a non-defense application. And we believe, hopefully, the start of other non-defense applications as well. The other one I will mention is Epson, right? We gave Epson more airtime today in the call based on that blog. That is also an example of a non-defense use. So, you know, it has been a while getting to more commercial customers, but I think we are starting to see a little bit more momentum and interest there now that we have these other process technologies supported.

Neil Young: Thanks. That makes sense. The other question I had, I am just interested in the competitive dynamics. So you talked about the potential storefront business being pretty large for this discrete strategic RadHard FPGA during the coming year and the year after that. I was curious if the competition differs at all from, you know, your traditional eFPGA IP that you have talked about. So just anything different on the competition front would be helpful, just understanding that.

Brian Faith: Sure. So if we go up to 50,000 feet and we say what is the programmable logic umbrella in total, there is eFPGA and there are FPGAs. And most people know the FPGA competitors—or I guess the peers, if you will, some of them not really competitors—would be Xilinx and Altera, and the FPGA division at Microchip, and Lattice, and Achronix and Achronix. Those are sort of the companies that do discrete FPGA devices.

Now, of those, if we think about what are the ones that are U.S.-based and have a defense focus and do devices that would fall into this category of some level of radiation hardness, you can kind of go and zoom in and say, okay, well, today Microchip has devices from their Actel acquisition long ago that do RadTolerant, to some extent RadHard, Xilinx has some RadTolerant, I think one RadHard device, I think Altera has some of it. I admit I have not looked at their product portfolio recently. And I think Lattice would like to get into defense and does not really have anything today in that area. I do not think Achronix does.

I think Achronix is mostly focused on Asia. So you are already whittled down pretty closely to just a couple of people that do any level of serious radiation hardness or tolerance. But when you compare and you say, okay, well, let me move the bar and say it has to be manufactured onshore and it has got to meet strategic levels, I would challenge anybody to go to the websites of those companies I just mentioned and point to a device that meets those requirements. I think it is an all set. So I think we are really well positioned in that sense as we continue to execute on this program.

Now, the other part of the programmable logic umbrella, as I mentioned, is eFPGA IP. And none of those companies that I just mentioned have real eFPGA IP. They want to sell you devices because they view IP as undermining device sales, I would imagine. From an IP perspective, there are really just a couple companies that have done IP in the last few years besides QuickLogic Corporation. One is called Flex Logix that was acquired last year by Analog Devices and made captive, so they do not do licensing anymore. Another is a French startup company called Menta, and they have licensable IP.

And then there are a couple really tiny academically oriented companies that I will not even give airtime to today. If you compare us against one company, Menta, again, I go back to we are a more established company, we are doing business with all these big companies. We have the spectrum of IP to devices. We are a U.S. company, products made in the U.S., so we have a lot of, I would say, differentiation at that level compared to Menta. The more important one is when you dig into the technical details, Menta is a soft IP company.

And so, IP means that when you are licensing IP to a customer, they are not just getting soft IP, they are getting a big boatload of work to make it a hard IP before they put it into their ASIC, and with that boatload of work comes a lot of risk and time and cost. And when you are a hard IP supplier like we are, we take care of all that. They do not have to worry about designing anything, they just need to think about how do I architect and use this IP? And so there is a huge difference in the engagement model between us and Menta.

And that is, I think, reflected in the wins that we are announcing, who is using us. It is also reflected in the average selling price of our IP, right? We are not doing soft IP that, you know, is a $20,000 IP that comes with a lot of work. You are licensing something for quite a bit more money, but we are taking care of that work and risk for the customer. And that is the huge difference between us and Menta as far as the eFPGA IP goes. Hopefully, that helps as an update on the competitive dynamics.

Neil Young: Yes. Very, very helpful. Thank you. Are all my questions.

Brian Faith: Welcome, Neil.

Operator: Our next question is from Tyler Bummeister with Lake Street Capital Markets. Please proceed.

Tyler Bummeister: Hey, guys. Thanks for letting me ask a few questions here. The next tranche of the U.S. SRH development program, the $13 million you got, as well as the announcement that the program had expanded with the GlobalFoundries process. Maybe it is a little bit of a follow-on from an earlier question. I think you said potentially in the high end of expectations this year, could see more funding. But, you know, to the extent you are able to, I am just wondering if you are going to be able to give any color on what next milestones we should be expecting or looking forward to from that program.

Brian Faith: So I am asked this question a lot, Tyler, and unfortunately, I cannot give programmatic details out on the program. But what I can say is I will go back to something I was given permission to say when we first got this contract in 2022, which is that the scope of this whole contract contemplates two devices, a test chip and a final chip. And so we were able to say, I think it was in the December press release when we announced the contract ceiling expansion to $89 million and adding GlobalFoundries, that we had in fact taped out a test chip for that contract.

So you can sort of check one off the list there of the two. So you can imagine—I think it is a natural extension that with more funding, especially the rate and the increase in the funding from this year over last year, and the fact we have already done one but not two chips, that we are embarking on that second chip development now. And, unfortunately, I am not going to be able to give really specific details on what is in the chip and when we are taping it out and when it is going to come out, but it is all in line with our obligations to the government for this contract.

Tyler Bummeister: Yep. That is perfect. Appreciate the extra color there. And then, you know, the full-year guidance was great, and I appreciate the details around that. You know, just putting the pieces together, strong Q1 and a number of initiatives kind of coming together at the same time here. Would it be reasonable to potentially expect some lumpiness through the year, maybe, you know, Q2 sequentially down? Or do you think you could grow revenue sequentially, you know, kind of linearly through the year?

Brian Faith: So we actually think that Q1 is going to be the low point for the year. Right? We will give that breadcrumb that the other quarters will be over Q1. There may be some lumpiness, and the reason why I say maybe is that when you are dealing with contracts that are, you know, $2–3 million each, especially if it is IP and it is recognized on delivery, then there is some natural lumpiness to when we get the contract, we make the delivery in a particular quarter. Right?

So there may be lumpiness from that perspective, but I think, you know, we are trying to give this outlook that Q1 is actually the low point for the year, that it is going to be up from here.

Tyler Bummeister: That is perfect. Appreciate that. Alright. That is all for me. Thanks, guys.

Brian Faith: Thanks, Tyler.

Operator: Our next question is from Gus Richard with Northland Capital Markets. Please proceed.

Gus Richard: Thanks for taking the questions. Just curious on Q3, you guys mentioned a million dollars commercial contract that you expected to revenue in Q4, it looked like you did. Is that part of the guide for Q1?

Brian Faith: No. It is not. In this call, we said that we are expecting or forecasting that to be contracted in Q2. And so that $3 million is not part of the Q1 guide. The other thing I will add, Gus, is when we said initially Q3 and then Q4, we said it may be in there or not, and it clearly got pushed. This is the one where we had said that now what they are looking at is a larger eFPGA core, and because they are looking at larger cores, they want to basically take more time on the technical feasibility side and diligence before we execute a contract.

That is not in the Q1 guide to be very clear.

Gus Richard: If I heard you correctly—the value contract was increased?

Brian Faith: Yeah. Well, we said the size of the core is increased. We did not say the value of it is increased, but the amount of eFPGA logic that they want is definitely larger than what they had originally thought of.

Gus Richard: Thank you. I understand. Yeah. And then my next question is for the test chip that you guys taped out and have gotten samples back, and you are getting orders for, you know, the test development boards. When do you expect those to start to ship? And, you know, how much revenue are you thinking you can generate, and from how many customers?

Brian Faith: Several questions in there. Let me unpack that. So, and for clarity, we have talked about two test chip tape-outs now, right, publicly. We have talked about the government-funded one. We have talked about the self-funded one. So because I cannot give updates on the government one by my obligations to the government, I can just talk about our self-funded one. So, on the self-funded one, we did receive the chips in Q1. I would say the fab was a little bit later than what we had planned on for that. Our engineering team is working on those chips right now and going through the validation process.

And what I have said previously is that as soon as we have those validated, then we will make sure that we can get those out to fulfill the test chip for the dev kit orders. And I think we had said previously, you know, we would love to get it out by the end of Q1. If it is into Q2, then that is fine too because we intentionally did this test chip tape-out so we gave ourselves a lot of buffer in terms of time for us to get these into the hands of the DIB, for them to do the evaluations that they need to do to get comfortable.

And I think your last question, Gus, there was how many customers. So the nature of this type of device being RadHard means that there are not a lot of people that you are actually allowed to sell it to. Clearly, U.S.-based. And the nature of this is really for the strategic defense systems, and there are only a handful of those that actually design for any kind of subsystem in those devices—or systems, I should say. So, you know, our target is less than five because those five really, really matter in terms of these major systems.

Gus Richard: Got it. Thanks for that clarity. And then my last one is on gross margins. You know, how do we think about the trajectory of gross margins going through the year? Non-GAAP, 45% for first quarter. Does that step up at all in the second quarter? And where—is it more of a linear ramp? How do we think about that?

Elias Nader: Q1 we said 45%, give or take. Q2 would most likely be around the same—flattish. And Q3 and Q4, I see an upside big time on gross margins. I have to say, over the time I have been here, this has been the most difficult piece of the puzzle to gauge and forecast, mainly because of the way we capitalize certain COGS and move certain things into OpEx and otherwise. So it has been a very tough exercise to do, but we are getting there. But overall, I see a decent 57% for the full year in terms of gross margin that I said in the script.

Gus Richard: Got it. I understand. Thank you so much.

Elias Nader: You are very welcome. Thank you.

Operator: Our next question is from Rick Neaton with Rivershore Investment Research. Please proceed.

Rick Neaton: Thank you for taking my question. I just had one question about chiplets. And you are talking about your bridging technology that you have used in the past with programmable logic. How do you see these chiplet applications using programmable logic, and what end uses are some of these being contemplated? And the second part of the question is on bridging. Are you talking about bridging on the chiplet or between chiplets?

Brian Faith: Two questions there. One is really the use case end applications for chiplets. And then one is, I guess, how are they partitioned within these packages? Is it all resident in one chiplet, or is it multiple chiplets to solve the problem? Right?

Rick Neaton: Right. Right. Are you bridging between layers on a chiplet or are you bridging between multilayer chiplets?

Brian Faith: Yep. Okay. I am just curious. I think—yeah. No. I can elaborate on some of this. So on the—let us start with the end markets and use cases for the chiplets. So I think we have talked about this before, but aerospace and defense is a really big market for chiplets because they do not want to have to do a bunch of custom ASICs if they can avoid it because their volumes are not terribly large, and it costs a lot of money to go off and do these custom ASICs. So to the extent they can make things heterogeneous inside the package, it is going to really help offset their program costs for development.

So the eFPGA in that case—you can almost look at where are FPGAs used today in those systems, and that becoming a chiplet and connecting them with other devices that they interface with in those systems today. So those systems today generally have some sort of big processor—could be a flight computer. The FPGA technology today is very useful for signals that are coming in from sensors, doing preprocessing on those signals, and packetizing them in a way that the actual CPU or SoC can process on without having to redo a lot of that capability that the FPGA is doing. Because remember, FPGAs are very good at real-time, highly parallelized computation.

So that is sort of the overall defense use case for these. And again, you can imagine that there is a lot of software that is already been written in the defense industry for certain processor architectures. There is already a lot of FPGAs used. Those die or capabilities inside one package actually save on the A and PPA, which is area, right? A lot of these systems are going for more miniaturization, and they are looking at packaging these things in a single package to do that. So that is the big use case there.

I would say outside of defense, there is a lot of interest for security or things that are sort of protected from this post-quantum era of computing for really just protecting systems from a cyber perspective. And eFPGA or FPGA is good for that because in the event that anything is hacked in the future, if the hardware itself is programmable, then you can reprogram whatever algorithm that you have in those to adapt to that threat at the time. And so there is interest in that as far as making these systems more trusted. And I do not mean trusted from a defense perspective.

I mean trusted in the sense that you can trust that it is running what it is supposed to be running and nothing more than that. That is also an interesting use case that is coming up for eFPGA chiplets. Again, the same idea being they have got a lot of software and infrastructure already. How can they adapt that existing infrastructure by adding a little bit of programmability and not redesigning all the ASICs? So that is a good use for an eFPGA chiplet. Now as far as the bridging goes, you can see from these examples that we are not replacing the whole SoC with this eFPGA.

It is basically taking the capability with the discrete FPGA and getting it inside the same package as what the SoC is or the ASIC is in their system architecture. And then as far as the actual bridging goes, you know, chiplets is kind of like if you go back to when USB or PCI was first being broadly adopted in the PC or laptop era of growth. That sort of happened—that was successful because everybody was able to standardize on a common interface, right? PCI is PCI, USB is USB. You design a peripheral with that, you go to the plug test, everything works, everybody is happy.

In chiplets, it is a lot more complicated than that because you have these different flavors of UCIe, as an example, and you have BOW, and they are incompatible. And so there is not this notion of, like, universal compatibility. Then if you dig even further into the details, if you want to, there is a difference between the physical layer and the protocol layer, right? So you can imagine a physical layer is me writing a note on a piece of paper and passing it to you, right? I pass the paper, you receive it, we are all good.

But if I am writing in a different language than what you understand, it would look like gibberish when you try to read that paper. The same thing is happening with UCIe where the physical layers may be compatible—right, UCIe cores on both sides—but the protocol that people are putting over UCIe are different. That is exacerbated by people doing ASICs at different points in time. So one of the things with our eFPGAs, we are thinking, well, that hardware is actually programmable.

So as long as the physical layers are connecting and as long as you have enough gates in our FPGA, you can probably program them to add some level of compatibility or, in my paper analogy, like a translator. And so we are hopeful that some of those will actually come to fruition based on that value proposition, and we are starting to get some positive feedback on that idea based on what we heard at the Chiplet Summit last week, and I think what we are going to hear at GOMAC next week in Louisiana when we are there presenting. Does that help with the use cases?

Rick Neaton: Yeah. No. I appreciate the color. And thanks for your time in answering my questions.

Brian Faith: Yeah. No problem. Awesome. Pleasure.

Operator: Our final question is a follow-up from Richard Shannon with Craig-Hallum Capital Group. Please proceed.

Richard Cutts Shannon: Hey, guys. Just one last question for me. Brian, again, hitting on the topic of strategic RadHard. Actually probably want to extend this maybe to RadHard given your comments on the call today here. But how many distinct programs are you bidding on here? I know you are not going to tell us an exact number, but I was hoping you could use language—a couple, a few, several, over a dozen—that sort of thing here. Just help us get a sense of number of programs you are bidding on. Thank you.

Brian Faith: I would say the immediate ones that are the highest level of radiation hardness, they are less than five major programs, but there are several subsystems within each major program that we would like to be inserted into. So I guess what you care about there is the total number of socket opportunities in that kind of parlance, and that would be, I do not know, 10 to 20 total? And that is for the highest level of radiation. It has been our focus because that is the greatest area of differentiation. If you start relaxing the radiation hardness requirements, obviously you can get into a lot of new applications around space.

And there are going to be tens of applications in space. But the initial focus for these first dev kit orders is going to be the ones that are higher levels of radiation where we do not have a competition at this point.

Richard Cutts Shannon: Got it. That is great perspective, Brian. That is all for me. Thank you.

Operator: There are no further questions. I would like to turn the conference back over to Brian Faith for closing remarks.

Brian Faith: Thank you. And we will provide a technical presentation on our chiplet POC at the Intel Foundry's Partners presentation at the upcoming GOMAC, March 10, together with Cadence and Trusted Semiconductor Solutions. In April, we will exhibit at HEART, which is another government radiation effects oriented conference, and also exhibit and present at IPSoC Days in Silicon Valley, again in April. Thank you for your support and for joining us today, and we will talk with you next time. Thank you. Goodbye.

Operator: Thank you. This will conclude today's conference. You may disconnect at this time, and thank you for your participation.

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