QuickLogic (QUIK) Q3 2025 Earnings Call Transcript

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Date

Nov. 11, 2025 at 5:30 p.m. ET

Call participants

• President and Chief Executive Officer — Brian Faith
• Senior Vice President and Chief Financial Officer — Elias Nader
• Managing Director, Darrow Associates — Alison Ziegler

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Risks

• Q3 non-GAAP gross margin was negative 11.9%, primarily due to unfavorable absorption of fixed costs on lower revenue and allocation of $300,000 in R&D costs to COGS.
• Annual revenue decline for 2025 is now projected at 20%-30% compared to 2024, with management attributing this to significant IP contract timing shifting into 2026.
• Q4 revenue guidance includes material risk from timing of a nearly $3,000,000 contract award, which, if delayed, would lower revenue for the quarter to $3,500,000, affecting recognized revenue and gross margins.
• Funding delay for mid 7-figure DIB contract targeting Intel 18A, originally expected in 2025, now deferred into 2026 with limited customer visibility on timing.

Takeaways

• Total revenue -- $2,000,000 in Q3, down 52.5% year over year and down 45% sequentially from Q2 2025.
• New product revenue -- $1,000,000, down 73.1% year over year and down 67.3% sequentially; Mature product revenue -- $1,100,000, increased from $700,000 in Q3 2024 and $800,000 in Q2 2025 (subtotal math offset explained in the transcript).
• Non-GAAP net loss -- $3,200,000, or $0.19 per diluted share, greater than $900,000, or $0.06 per diluted share, in Q3 2024, and $1,500,000, or $0.09 per share, in Q2 2025.
• Non-GAAP operating expenses -- $2,900,000 for Q3, $300,000 below midpoint guidance, primarily due to R&D cost allocation to COGS.
• Cash balance -- $17,300,000 as of quarter-end, including $15,000,000 utilized from the $20,000,000 credit facility; quarterly cash usage was approximately $1,900,000, mainly for SRH FPGA test chip wafer costs and tooling.
• Q4 revenue guidance -- Targeted at $3,500,000 to $6,000,000, driven by timing of a forecasted commercial contract near $3,000,000; if the contract is delayed, only $3,500,000 would be recognized, not $6,000,000.
• Q4 non-GAAP gross margin outlook -- Expected to be approximately 45% at $3,500,000 revenue and 68% at $6,000,000; the range is driven by absorption of fixed costs and contract timing.
• Storefront revenue -- Management said, "meaningful" for 2026 and estimated to be in the "10% range" of total company revenue.
• SRH FPGA test chip program -- Test chip delivered to GlobalFoundries for fabrication on 12LP, with customer dev kits expected to ship in Q1 2026 and early commitments already received.
• Major contract awards -- Secured multiple contracts with large defense customers in 2025, including a $1,000,000 feasibility study and follow-on orders targeting Intel ATNA with high-density eFPGA blocks.
• EF hard IP contract -- Announced new $1,000,000 contract for a high-performance data center ASIC on TSMC 12nm, with QuickLogic's eFPGA as primary IP.
• Q4 non-GAAP operating expense guidance -- Approximately $3,000,000, plus or minus 5%, with full-year 2025 non-GAAP OpEx projected at $11,300,000.
• Stock-based compensation -- $800,000 in Q3, consistent with Q2, and projected at the same level in Q4 2025.
• Cash flow expectations -- Anticipated to remain positive in Q4 at both the low and high end of revenue guidance, except for risk of delayed US Government contract payments.
• Employee expansion -- Three engineering hires targeted, with OpEx expected to be $3,500,000 per quarter starting Q2 2026 if headcount increases as planned.
• Customer diversity -- Two customers accounted for 10% or more of total Q3 revenue.

Summary

QuickLogic (NASDAQ:QUIK) reported sharply lower Q3 revenue and gross margin driven by a significant decline in new product sales and allocation of R&D expenses to cost of goods sold. Management highlighted expansion in high-value eFPGA design contracts, notably in defense and data center applications, while providing a Q4 revenue outlook highly sensitive to the timing of a large commercial contract award. Storefront and SRH FPGA initiatives progressed with new customer commitments, though the timing of substantial government contract revenue has shifted into 2026, amplifying year-end results variability. Cash position remains stable, helped by ATM proceeds and capex discipline, while operating expense levels are expected to rise modestly to support growing engineering demands.

• President and CEO Faith said, "license revenue may surpass NRE revenue for the first time this quarter," indicating a revenue mix shift potentially favorable for margin improvements as licensing scales.
• The company expects to recognize SRH storefront revenue in early 2026, which management emphasized as a new and distinct source versus legacy contract revenue.
• A mid 7-figure defense industrial base (DIB) contract targeting Intel 18A is now delayed into 2026, which management explicitly said impacts 2025 annual revenue.
• QuickLogic's Q4 net income guidance ranges from a non-GAAP net loss of approximately $1,900,000 (or $0.11 per share) at the low end of revenue to a non-GAAP net profit of $600,000 (or $0.04 per share) at the high end, reflecting the significance of contract timing to profitability.
• Faith stated that being able to design with the Aurora user tools for both discrete FPGAs and eFPGA hard IP is a key differentiator for DIB customers.
• The digital FPGA chiplet proof-of-concept successfully completed its first phase, supporting an accelerated route to commercial chiplet and defense opportunities pending external funding for further development.
• Management described high demand for the newly fabricated SRH FPGA test chip, with customer dev kits ordered and shipments targeted for early next year.

Industry glossary

• eFPGA: Embedded Field Programmable Gate Array; logic blocks implemented as IP within ASICs, enabling re-programmability post-manufacture.
• SRH FPGA: Strategic Radiation Hardened Field Programmable Gate Array; FPGAs designed for high resilience in defense and aerospace environments.
• DIB: Defense Industrial Base; companies providing products for military, defense, and national security applications.
• NRE revenue: Non-Recurring Engineering revenue, derived from custom contract work, typically one-time in nature.
• Storefront: QuickLogic's business model offering standardized FPGA products to multiple customers versus purely custom/licensed IP.
• 12LP/12OP process: 12-nanometer Low Power (GlobalFoundries) fabrication node used for advanced and radiation-hardened chips.
• Dev kit: Development kit; hardware and software provided for customer evaluation and design prototyping purposes.

Full Conference Call Transcript

Operator: Ladies and gentlemen, good afternoon. At this time, I would like to welcome everyone to the QuickLogic Corporation's Third Quarter Fiscal 2025 Earnings Results Conference Call. As a reminder, today's call is being recorded for replay purposes through November 18, 2025. I would now like to turn the conference over to Miss Alison Ziegler of Darrow Associates. Miss Ziegler, please go ahead.

Alison Ziegler: Thank you, Bon, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including, but not limited to, statements regarding our future profitability and cash flows, expectations regarding our future business, and statements regarding the timing, milestones, and payments related to our government contracts, statements regarding the use of the company's ATM program, and statements about our ability to successfully exit Central.

Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low power, competitive pricing, and short time to market of our new products, intense competition from competitors, our ability to hire and retain qualified personnel, changes in demand or supply, general economic conditions, political events, international trade disputes, natural disasters, and other business interruptions that could disrupt supply delivery of or demand for the company's products, and changes in tax rates and exposure to additional tax liabilities.

For more detailed discussions of the risks, uncertainties, and assumptions that could result in those differences, please refer to the risk factors discussed in QuickLogic's most recently filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information, which speak as of their respective dates of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We've also posted an updated financial table on our IR webpage that provides current and historical non-GAAP data.

Please note QuickLogic uses its website, corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR webpage shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.

Brian Faith: Thank you, Alison. Good afternoon, everyone, and thank you all for joining our third quarter 2025 conference call. We have made very significant progress since our August conference call. Last quarter, I stated that we focused considerable engineering to accelerate storefront design wins for our strategic RadHard FPGA and expand our served available market to very high-density eFPGA hard IP designs targeting advanced fabrication nodes. I'm proud to say our engineering team has executed beautifully, and we are realizing these goals. We expect to begin recognizing storefront revenue in early 2026, and that it will provide a meaningful contribution to total 2026 revenue.

The interest from large defense industrial base entities or DIBs in the SRH test chip we funded is notably higher than I anticipated. We have significantly expanded our ability to address the lucrative markets for very high-density, discrete FPGAs and ASICs that require large blocks of eFPGA. New contracts and engagements are for much larger blocks of eFPGA and on advanced fabrication processes. The value contribution of eFPGA in customer designs has grown substantially. Our penetration in commercial market sectors is expanding, and with this progress, the rate of new contract closure is accelerating to the point that license revenue may surpass NRE revenue for the first time this quarter. We believe these trends will accelerate going forward.

Before I get into the tangible data that support these points, I want to take a moment and provide some color for the revenue guidance Elias will share in his presentation. Based on our backlog and forecast provided to us by our customers, we are targeting total revenue of $6,000,000 for Q4. The majority of the contracts that support this outlook are already on the books or have been forecasted by customers to be awarded during the coming weeks. However, a contract valued at nearly $3,000,000 for a commercial application targeting an advanced fabrication node has been forecasted by the customer to be awarded late in the quarter.

If this contract is awarded on or very near the date forecasted, we will be able to recognize a large portion of that revenue in Q4, and with that, realize our $6,000,000 objective. We have a very high level of confidence in winning this contract, but note that it could push into Q1 2026, and that would result in lower Q4 2025 total revenue. Due to this, Elias will present an unusually wide guidance range. And now let's walk through our accomplishments. In early August, we delivered design files to GlobalFoundries to fabricate our SRH FPGA test chip using its 12 LP process.

This test chip was designed to meet the requirements of certain large DIBs that have programs in development today that are good candidates for this device. We expect delivery of test chips in early Q1 2026 and believe we will have our SRH dev kit ready for shipment to customers shortly thereafter. This initiative was financed by QuickLogic and is independent from our contract with the US government. Our decision to invest the money and resources to develop this test chip was based on our belief that it is critical in our quest to secure strategic design wins and accelerate our storefront business model.

Since our last earnings conference call, I have personally met with a number of the DIBs that worked with us through the development process, and I cannot emphasize enough the potential of our SRH storefront initiative. In prior meetings, all I had to show were PowerPoint presentations, and now with a test chip in fabrication, the level of enthusiasm is palpably higher. As a matter of fact, we already have commitments for SRH dev kit orders that we expect to receive by the end of this month. I see this as our first tangible step towards the hundreds of millions of dollars in potential storefront business we can win in the coming years.

The importance of demonstrating our SRH FPGA test chip goes well beyond the storefront designs we believe it will enable us to secure. FPGA is the number one spend category for semiconductor devices by the defense industrial base, and custom ASICs are a close second. Together, we believe these two categories make up roughly half of the DIB semiconductor TAM. We expect many of the new strategic designs that require various levels of radiation hardness will use either discrete FPGA devices that we can storefront or eFPGA hard IP we can license in new ASIC designs.

By delivering a discrete SRH FPGA test chip fabricated on 12OP process, we are demonstrating the broader capability of our eFPGA hard IP for ASIC applications that will meet program requirements ranging from radiation tolerant to strategic RadHard. There are three very important points I want to highlight here. First, DIBs are already using GlobalFoundry's 12 o fabrication process for radiation tolerant and SRH ASICs. Second, government contracts require the use of onshore fabrication for strategic programs when devices are available. As it stands today, we will be the only source for strategic RadHard FPGAs and SRH eFPGA hard IP that is fabricated in the US by a US company.

Third, in my meetings at large DIBs, engineering managers have clearly stated that being able to design with our Aurora FPGA user tools for both our SRH discrete FPGAs and our eFPGA hard IP and ASIC designs is a huge plus. During our last conference call, I stated that Q3 would mark the low point for revenue recognition for our US Government SRH FPGA contract this year. Funded by the current tranche, revenue recognition from the contract will rebound significantly in Q4. Beyond that, we anticipate an increase in quarterly revenue recognition in 2026 that will be funded by the next tranche.

During our last conference call, I forecasted the award of a mid 7-figure contract from a DIB during Q4 that targets Intel 18A. Unfortunately, there has been a delay in funding that pushes this contract into 2026. We are highly confident that we'll be awarded this contract, but at this juncture, our customer has limited visibility on the timing of funding. While we await funding for this 7-figure deal, it is worth noting that we have already been awarded multiple contracts by this strategic customer during 2025. We delivered customer-specific eFPGA hard IP for this customer's first Intel ATNA test shipped last April.

We expect to receive our allocation of test ships from this contract during Q1 2026 for our internal verification and characterization. We were subsequently awarded a mid 6-figure contract for a second Intel ATNA test chip. We delivered customer-specific eFPGA hard IP for this test chip during Q3. In addition to these Intel ATNA test chip contracts, during our last conference call, I announced this customer awarded us a contract for a $1,000,000 feasibility study that we are scheduled to deliver next week.

We are anticipating a follow-on order in the coming weeks associated with this feasibility study that will enable the customer to tape out a very high-density Intel ATNA proof of concept device during the second half of 2026. The architectural changes we implemented in this feasibility study can be leveraged across all advanced fabrication nodes, which we define as 12 nanometers and below. With these changes, we can now address the lucrative markets that require very high-density eFPGA blocks in ASIC design and very high-density discrete FPGAs. This significantly expands our SAM for eFPGA hard IP and discrete devices, including our SRH FPGA, chiplets, and other storefront opportunities.

We initiated our digital proof of concept chiplet program earlier this year as a strategy to accelerate our storefront chiplet initiative. Internally, we refer to this as POC. With the support of our large strategic partners, we have leveraged our existing eFPGA hard IP and readily available third-party IP to move forward rapidly and with minimal investment. In line with the forecast I shared in our last conference call, we completed the initial phase of the digital FPGA chiplet POC where the eFPGA IP is connected to UCIE IP and the necessary interface logic for the IPs to communicate. This digital simulation of the POC is available now and can be further developed to meet different customer requirements.

Together with our ecosystem partners, we are engaging with prospective customers in the defense aerospace, industrial, and commercial markets. We plan to move forward with the next phases of the FPGA chiplet POC once external funding is committed. This phase will include incorporating additional IP, such as programmable GPIOs, AXI bus, DSPs, data converters, and interfaces such as PCI Express, to meet specific customer requirements. We are optimistic that our POC initiative will lead to storefront revenue in 2026. On October 2, we announced a new $1,000,000 EF hard IP contract for a high-performance data center ASIC that will be fabricated on TSMC's 12 nanometer process.

In this ASIC, our eFPGA hard IP will be the primary IP in the design. This contract is a great illustration of our success in several of the points I mentioned earlier. The need for larger blocks of eFPGA, the increasing value contribution of eFPGA in customer designs, winning contracts for designs targeting advanced fabrication processes, and our growing success in commercial market sectors. We will soon announce the expansion of our involvement with a DIB that specializes in cybersecurity for strategic and tactical weapon systems. This DIB designs secure system-on-chip processors that leverage the enhanced security that only eFPGA can provide. Running these processes in hardware is inherently more secure than software solutions.

With eFPGA at the heart of the designs, the hardware can be altered to respond to new threats and updated algorithms. We are proud to have been chosen as a trusted supplier of eFPGA hard IP for these designs. Last April, we announced an eFPGA hard IP contract with a new defense industrial base customer valued at $1,100,000 that will be fabricated on the GF12LP process. This application utilizes a large block of our eFPGA hard IP for critical functions, which is a trend we are seeing, particularly in designs targeting advanced fabrication nodes.

With the cooperation of this DIB and its end customer, we are leveraging the large eFPGA core into a new 7-figure contract we expect to announce in the coming weeks. In the scope of this new contract, we will be provided with test chips that we will incorporate in an evaluation kit. The evaluation kit will be compatible with common third-party development environments used by both 12 o p test chip or our eFPGA hard IP in an ASIC. We anticipate having evaluation kits available in late 2026. With that, I will turn the call over to Elias for his presentation of financial data.

Elias Nader: Thank you, Brian, and good afternoon, everyone. Total third quarter revenue was $2,000,000 and aligned with the midpoint of our guidance. Total revenue was down 52.5% from Q3 2024 and down 45% compared to Q2 2025. Rounded to the nearest $100,000, new product revenue in Q3 was $1,000,000 and mature product revenue was $1,100,000. New product revenue was down 73.1% from Q3 2024 and down 67.3% compared to Q2 2025. Mature product revenue was up from $700,000 in 2024 and up from $800,000 in 2025. Non-GAAP gross margin in Q3 was a negative 11.9%. This compared with non-GAAP gross margin of 65.3% in Q3 2024 and 31% in Q2 2025.

The primary reasons for the lower Q3 gross profit margin are unfavorable absorption of fixed costs due to lower revenue and the fact that $300,000 of R&D cost were allocated to COGS. Non-GAAP operating expenses in Q3 were approximately $2,900,000. This was approximately $300,000 below the midpoint of our outlook due to the COGS allocation I just mentioned. This compares with non-GAAP operating expenses of $3,300,000 in 2024 and $2,500,000 in 2025. Non-GAAP net loss was $3,200,000 or $0.19 per diluted share. This compares to non-GAAP net loss of $900,000 or $0.06 per diluted share in Q3 2024 and a non-GAAP net loss of $1,500,000 or $0.09 per diluted share in 2025.

The difference between our GAAP and non-GAAP results is related to non-cash stock-based compensation expenses, impairment charges, and restructuring costs. Stock-based compensation for Q3 was $800,000. Stock-based compensation was $1,200,000 in Q3 2024 and $800,000 in Q2 2025. Impairment charges were $300,000 in Q2 customers accounted for 10% or more of total revenue. At the close of Q3, total cash was $17,300,000 inclusive of utilization of $15,000,000 from our $20,000,000 credit facility. This compares with $19,200,000 inclusive of usage of $15,000,000 from our $20,000,000 credit facility at the close of Q2 2025. Net of approximately $200,000 raised with our ATM in July, cash usage during Q3 was approximately $1,900,000.

This was primarily driven by tip-outs and wafer costs associated with our internally financed SRH FPGA test chip. In addition to these one-time costs, there were also expenditures related to revenue contracts and repayments for finance tooling and equipment. Now moving to our guidance and outlook for our fiscal fourth quarter, which will end on December 28, 2025. Based on backlog and customer forecast, we are targeting total revenue of $6,000,000 for Q4. Many of the contracts that support this outlook are already on the books or have been forecasted by customers to be awarded during the coming weeks. However, the customer for a contract valued at nearly $3,000,000 for commercial application has forecasted the award late in the quarter.

If this contract is awarded, on or very near the date forecasted, we will be able to recognize a large portion of that revenue in Q4, and with that, realize our $6,000,000 objective. We have a very high level of confidence in winning this contract but note that it could push into Q1 2026. And that would result in Q4 revenue of $3,500,000. Due to this, our guidance range for total Q4 revenue is $3,500,000 to $6,000,000. At $3,500,000, we expect total revenue to be comprised of $2,500,000 in new product revenue and $1,000,000 in mature product revenue. At $6,000,000, we expect $5,000,000 in new product revenue.

Based on the anticipated Q4 revenue mix, non-GAAP gross margin for the fourth quarter is expected to be approximately 45% at $3,500,000 of revenue and 68% at $6,000,000 of revenue. At the low end of the range, the primary reason for lower gross profit margin is attributed to less favorable absorption of fixed costs. Taking the range of our Q4 outlook into consideration, our full year 2025 non-GAAP gross profit margin is expected to be 38% plus or minus 5%. Our Q4 non-GAAP operating expenses are expected to be approximately $3,000,000 plus or minus 5%. With this, we are modeling full year 2025 non-GAAP OpEx would be approximately $11,300,000.

Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS versus OpEx, or capitalize certain costs. These classifications are related to labor and tooling for IP contracts with customers. This may cause variability in our quarterly gross margins and operating results that will usually balance out on the operating line. After interest and other income, at the low end of the revenue range, we forecast a Q4 non-GAAP net loss of approximately $1,900,000 or $0.11 per share. At the high end of our revenue range, we are projecting a non-GAAP net profit of approximately $600,000 or $0.04 per share.

The main difference between our GAAP and non-GAAP results is related to non-cash stock-based compensation expenses. In Q4, we expect this compensation will be approximately $800,000. This is the same as Q3 2025 and down slightly from Q4 2024. As a reminder, there will be movement in our stock-based compensation during the year, and it may vary each quarter based on the timing of grants. Even at the low end of our revenue guidance range, we anticipate cash flow in Q4. However, the timing of payments from our US Government contract could negatively impact this outlook.

Given the fact that we raised approximately $2,000,000 using our existing ATM in October, we're well prepared for any delayed payments associated with the US government contract. Thank you. With that, let me now turn the call over to Brian for his closing remarks.

Brian Faith: Thank you, Elias. We have logged considerable progress during the last few months, and we are leveraging that progress to produce tangible results. Earlier, I talked about those results, and now I would like to take the next few minutes to help you understand the industry trends that are driving these results. With that understanding, I think you will appreciate what is driving the increased interest in FPGA technology, and why more companies are incorporating larger blocks of at the core of new ASIC designs. The overarching trend in both commercial and DIB designs is smart systems. Smart systems rely on algorithms for their intelligence.

Algorithms can be processed much faster and with much lower power consumption in hardware than software. Hardware processing is also inherently more secure against cyber threats than software. The challenge here is that algorithms must be updated over the lifecycle of the product. This means hardware must be programmable so it can adapt to changing algorithms. This has led to the need for larger blocks of eFPGA at the heart of ASIC designs versus past use cases where small blocks of eFPGA were more commonly used as programmable connectivity bridges. This means both the need and the value proposition for eFPGA are increasing. Sophisticated smart systems designs typically target advanced fabrication nodes.

This means higher fixed costs and longer design cycles for ASICs. To favorably offset these higher fixed costs, ASIC designs must deliver longer life cycles than in the past. Designs that employ eFPGA can adapt to changing algorithms, evolving functional requirements, and external changes that are not evident during the design cycle. This flexibility lengthens the lifecycle of ASIC designs and provides program managers with the confidence to move ASICs to production more quickly and with lower risk. This shortens design cycles and lowers development costs. Last but certainly not least, there are many programs in development today that must be compliant with rigorous environmental requirements ranging from radiation tolerant to strategic RadHEART.

Our internally funded development of an SRH FPGA test chip is designed to address the full range of these requirements and accelerates our ability to pursue design wins. By using the same onshore 12OP fabrication process that DIBs have used for SRH ASICs, we are optimizing our chances of winning discrete FPGA designs we can storefront and contracts for eFPGA hard IP that customers can incorporate in designs. Further enhancing our position is the fact customers can execute designs with our Aurora user tools for both.

The fact this investment by QuickLogic has been received very well by strategic DIBs is underscored by the commitment we have for SRH dev kit orders that we anticipate receiving by the end of this month. Before I turn the call over for Q&A, I want to take a moment to recognize Veterans Day and express my heartfelt gratitude to all those who have served our country. This day has personal meaning for me, as several members of my family have served, and I have deep respect for the sacrifices made by veterans and their families. It's something we honor at QuickLogic, especially as we develop technologies that contribute to our nation's defense and security.

Operator, I would now like to open the call for questions.

Operator: Thank you. We will now be conducting a question and answer session where selected analysts will be invited for questions. If you would like to ask a question, please press 1 on your telephone keypad. A confirmation tone will indicate your line is in the question queue. You may press 2 if you would like to remove your question from the queue. It may be necessary to pick up your handset before pressing the star keys. Our first question comes from Quinn Bolton with Needham. You may proceed with your question.

Neil Young: Hey, everyone. It's Neil Young on for Quinn Bolton. Thank you for letting me ask a question. First question I wanted to ask, hey. That's you know, like I said, on for Quinn. Sorry about that. So what is the or what impact is the government shutdown having on your business? Based on the prepared remarks, it sounds like you've seen some delays of projects. Have you seen any cancellations? And then, you know, given the ongoing shutdown, although it is allegedly supposed to end soon here, what gives you confidence in a rebound of the US strategic radiation Arden FPGA program in 4Q? Then I have a follow-up. Thanks.

Brian Faith: Yeah. I think, firstly, let's zoom out. Programmable logic has been a big part of the defense industrial base for decades, and that's not changing. It's pervasive across, like, 75% of defense systems. And as I mentioned earlier, a very large percentage of the total semiconductor spend by the DoD. So that demand is not going away. The question is, as you get down to the nuts and bolts of these programs, is the funding gonna be there based on the budgets and whatnot? So I think that from the programs that we have today on contract, we're not seeing any delays with those.

Elias did mention in his conversation about the cash usage for the quarter, or I should say net cash gain in the quarter. We did use the ATM in October sort of as anticipation in case there was something like this that happened as far as funding goes. So if there's a delay in funding, then we have no issue with that. If there's no delay, then we'll have a good positive cash flow for the quarter. Aside from that, if you look at other contracts coming down the pipe, I mean, you could find this all publicly that a lot of the new RFIs or RFSs or RFT that were coming out from the government for various development programs.

Some of those were actually paused. And I think that's largely because some of those workers that were driving that were put on furlough. Again, I don't anticipate those going away permanently. It's more once the government's funded and people get back from furlough, these are gonna be full steam ahead. So you might see a delay in some of those new programs but not the ones that we're fully executing on today. I just don't see that change because this is not an experimental technology. There are actual programs of record that need this today. And moving forward on that. Does that answer your first question?

Neil Young: Yeah. Very helpful. Thank you. And then the second question I wanna ask. So sounds like storefront revenue in 2026 is supposed to have a meaningful step up. If possible, I was wondering if you can maybe size the range of storefront revenue you think is possible. And then know, if not, maybe could give us some idea of what could drive upside to your internal you know, on the other side, perhaps drive downside to those expectations? Thanks.

Brian Faith: Sure. I'll start with the what, and then I'll answer with the why. So on the what side, I mean, I would say significant for us is gonna be the 10% or thereabouts of total revenue. Without giving the exact number because we haven't put numbers out for 2026 yet, we think that the storefront revenue associated with these developments that we've been talking about is gonna be meaningful, meaning it'll be in that 10% range. And, yes, I do think next year's revenue will be notably higher than this year's total revenue.

As you get into why do I feel like that, think if you go back to my opening remarks about the strategic radar initiative, I cannot tell you how many meetings I've had in the last quarter since the last conference call face to face with these DIBs. That see what we're doing, they like the fact that we've done this tape out that we talked about. And, you know, even as of today, lots of calls and emails asking for when they can get their hands on this. And so when you start to see people pulling for the technology and you know the projects that are under development public projects. Right?

Strategic defense system is going under a major modernization. That's all public knowledge. And then if you throw into that this notion of hypersonics and golden dome, a lot of these programs are gonna need some level from strategic radar down to radiation tolerant. The part that we've got in the fab now is designed to address those needs. So as we get it out, we start moving to these orders for dev kits. We start getting those out. Hopefully, by the end of Q1, I think we're gonna be a prime a real prime spot to monetize that and start turning talk that I've had for two and a half years into actual revenue and bottom line contribution.

But it's not just one here. We're talking about all the major DIBs that we've been talking to. I think there's good demand for that. So that's why we think it's gonna be meaningful for next year. Does that answer your question? Thank you.

Neil Young: Yes. Thank you very much. Great.

Operator: You're welcome. Our next question comes from Richard Shannon with Craig Hallum. You may proceed with your question.

Richard Shannon: Great. Thanks, Brian and Elias, for taking my questions. Quality of the audio here is pretty poor on my end, so hopefully you can hear me. Apologize. You can't hear. We can hear you just fine. Okay. Let's go. I guess at least one of us can. Lot of detail on the call here, and it's really interesting stuff going on here. Let me ask a kind of a big picture high-level question here. With your new initiative on the GF 12 LP process or initiative here. I guess, how do we think about the opportunity for FPGAs versus ASICs, it would include your hard IP in here.

And are the dynamics here for timing for each of these markedly different than the other?

Brian Faith: Well, I'd start by saying for 12 o p, that is a very commonly used process by the defense industrial base. Think the heritage of that is that was the most advanced process that GlobalFoundries had, and GlobalFoundries is US owned and operated. So if you wanted to have something that was manufactured onshore by a US company, that was sort of the most advance you can get. Global has since come out with 12 o p plus, which is in it more advanced version of 12 o p.

But if you think about what's involved in doing an ASIC or an SOC, you need lots of IP available, and you need lots of test data characterization on all that IP in order to feel comfortable to move forward with that on your ASIC. And in terms of the defense community, it's very risk-averse community as they should be. As they're designing these systems. There's a wealth of IP on 12 o p that there is it's today, it's known, it's understood, the characterization data, and the government, again, this is all publicly findable, the government has been, you know, helping people do ASICs on 12 o p. A lot of IP is available.

There's government-funded multi-project wafers and all those things to encourage development on that node. So from that standpoint, I think you're gonna see TOFO p a lot. You've seen it in the past. You're gonna see it in the future. So then the question for us is, okay. We have our IP on 12 o p. Now we can build devices from that, or we could build or we could license that for people doing their own ASICs. And I think we've already talked about IP licenses that we have on ASICs. And you've heard timing on that. So people will start to be taping out those and going to production hopefully in the next few years.

So there's a near-term license opportunity. There's a back-end royalty opportunity for us on that. And we definitely plan to monetize that to several million dollars a year. On the device side, that gets interesting because we've obviously taken our commercial total PIP, and we've done a RadHard implementation of that. So the goal behind that is to do this strategic RadHard FPGA and having taped that out.

If you fast forward to when we could do that actual product dive for production on that, once that's out, that's gonna be a significant step function increase in the revenue potential for us personally because devices of that nature are always gonna have a much higher ASP than what a royalty contribution would be. So I think total p is critically important for us. And it's sort of a land and expand strategy on that now where we wanna license it to as many people as we can. We wanna have this strategic router FPGA capture. For revenue, and that's, I think, the basis of what could be hundreds of millions of dollars in revenue.

I know if I answered your question. It's an entirety. If I didn't, just tell me.

Richard Shannon: Did for the most part. I'm just trying to circle around this a bit here from a very high level. Might ask another pretty high-level question here, Brian, which is comparing the opportunity you're you've now undergone with GFS 12 LP, or how do you compare the opportunity to what you've been doing with RadHard with other foundries you've announced with I guess, a total perspective over, I'll let you pick a time frame. But how do you see the relative size of each of these opportunities for

Brian Faith: By the other founders, you're referring to Skywater and Honeywell or somebody else?

Richard Shannon: Those are the ones. Yes. Okay.

Brian Faith: So I think without getting into programmatic details, I think that the 12 l p opportunity for us is a larger opportunity. Because it has the strategic pattern FPGA it also has IP licensing as an option. And one of the nice things, and I you know this, is that as you get smaller process technology, you get denser transistors you get more capability, you can stuff in a die, and there's gonna be higher value. To that. And we enumerate that as far as, like, where we're taking our eFPG architecture, but the same is true at 12 nanometer and 12 o p.

The more transistors and functionality we can stick on that dye, the higher the value of the part's gonna be. And I think, again, the interesting part about 12 o p here is that we can get a lot of capability running on our FPGA. 12 o p. And maybe somebody doesn't even need to do an ASIC now. For 12 o p. That's huge. If we can start helping people address the needs of admission without having to go off and do a custom ASIC, you're talking about saving a customer or the government literally tens of millions of dollars in years of development. Cost and time.

And that's the real benefit, I think, to getting our FPGA on 12 nanometer given that it's strategic at heart and so capable of a node. Now as you've talked about those other foundries, those are older process geometries that they've talked about. And so there's gonna be a difference in what you can do on the die. There's a difference in what you can do capability-wise. Not bad. It's just different. But I think the bigger bucket of revenue for us is gonna be what we're gonna be able to do at 12 nanometer on these for the time being.

And I don't wanna get into more details on that just because that's a little too much programmatic information if I go further.

Richard Shannon: Yep. I get that. Just that high level here is very helpful to think about. Brian, thanks for that. You mentioned expecting orders for your new dev kits here, I think, the end of the end of this month and delivering those sometime next year. Can you give us a sense of how many dev kits and how many customers do you expect to ship that to? And then what's kind of the design cycle once customers get that in hand in terms of their next steps?

Brian Faith: So I'm not gonna give numbers. Probably not surprised to hear that. But it's gonna be enough that it will be a significant revenue number so not just the rounding. Number on the income statement. And we've you know, Elias talked about the money that we spent in Q3 on that. We've intentionally bought enough DAI that we can provide enough for these customers that wanna test these things out both in terms of dev kit and on just raw devices themselves on their own boards. Now the way this works from an evaluation perspective again, this is a very cautious and risk-averse community that we're talking about.

They're gonna wanna do their own testing on these things, and that generally takes you know, a couple quarters to go off and do all of your exercising of your design and the different environmental tests that need to need to be done on those devices. You've probably read the TRL levels, technology readiness level. You know, we wanna get customers as quickly as possible to t r l five. And t r l five is where they can actually say that they've taken the part and they've run it through the rigorous testing that's representative of the environment that they're gonna operate in.

And so we hope to be able to support our customers to get through that at some point. Through the middle of next year, and then at that point, start intercepting actual programs of record with us. And moving into you know, pretty late stages of the design, hopefully, with them. And again, that's why time is so critical. That's why we took the leap of faith to do their own design and to fund our own tape out knowing that MPWs don't come along very often, we wanted to make sure that we're on one that still gave us enough time to have the part come out, verify it, and get into the hands of the DIB.

So they can start playing with it in their own labs. Not just trust our own data.

Richard Shannon: Okay. Great, great perspective there, Brian. Last question. I'll jump out of line. A lot of irons in the fire that you have going on here, which is great to see here. And QuickLogic, obviously, is a fairly small company here. Seems like it might need a bit more support to a broad range of customers coming your way here very soon. How do we think about the spend levels we need to see next year, you know, whether it comes through OpEx or stuff that gets allocated to COGS here. How do we think about where could go if things go really well and you get a lot of attention?

Lot of, lot of activity in these dev kits you're sending out.

Brian Faith: So I'll start answering, and I'll ask Elias to chime on those. So from an engineering perspective and the go-to-market team perspective, you know, we obviously have identified certain critical hires. Some of them, you could find on our website today, and these are all about getting the right resources to get the devices out into the hands of the DIB as soon as possible. I mean, you can find that on our website. Engineering, field application engineering, and so on. As we move from test chip to actual product chip, there will be more expenses. There will be other things that need to be paid for.

And I think that we have a good line of sight on what those are gonna be. And it's not gonna be outrageous for next year. I think it's gonna be very mindful of where we are. Financially as a company, and tied in with getting these customers on board with test jobs so that any investments we do make coming from the perspective of knowing what our customer wants, knowing the problem that our solution solves, and in some cases, even perhaps getting funding from customers to co-invest in these things so that they have skin in the game and it offsets the upfront cost for QuickLogic to get it to market.

Elias Nader: Yep. Correct. And in fact, Richard, if I may add like, example, we have three new hires we're looking for. All engineers. And as such, you know, OpEx is definitely headcount moderating. So I don't anticipate even with all the additions that Brian is describing, probably we'll be looking at probably 3 and a half million of OpEx per quarter probably next year, but starting in Q2 or so. I think for now, we're okay with about under three.

Richard Shannon: Okay. That's great detail, I will jump the line. Thank you.

Brian Faith: Thanks, Richard.

Operator: Before our next question, as a reminder, if any analysts like to ask a question, our next question comes from Rick Neaton with Rivershore Investment Research. You may proceed with your question.

Rick Neaton: Thank you. Hi, Brian, and hi, Elias.

Elias Nader: Hello, Rick.

Rick Neaton: I'd like to understand your Q4 guidance. Are you proposing an either-or situation where we're either gonna have 3 and a half million plus or minus or 6,000,000 plus or minus? Is that what you're saying?

Elias Nader: Yes. Because there's an issue with timing. Right? So if the order comes in, for example, to complete it to 6,000,000, it would come in late in the quarter. And we may be able to recognize certain portions of that revenue. But if it comes in and we're not able to deliver in that quarter, let's just say it comes in on the day of our close, of the day after, it's definitely Q1 at that point. So it's almost a timing issue, Rick. And that's why we went to great pains to identify the difference between 3 and a half million revenue and 6,000,000 revenue, and really it's one order. And as such, it's all about timing.

So it's very difficult to answer a question now to someone saying, okay, would you be able to recognize a 100% of it? And the answer is clearly no. If it comes in Q4. So that is why Brian and I agreed if that's the case and we anticipate that order coming in, let's just hope it does. At least in Q4, we at least have the possibility of beating the high end of the range.

Rick Neaton: Thank you for that explanation. Sure. What do you forecast as your share count for 2025?

Elias Nader: Well, $1,717,090,252 thousand shares. That's all I've outstanding right now.

Rick Neaton: Okay. One final question.

Elias Nader: Yeah.

Rick Neaton: Yeah. No. That's fine. So that's your ending share count would be $17. Three months ago, you described your expected revenue decline for 2025 with the adjective modest. And now your Q4 guidance suggests 2020 to 30% decline in annual revenue from 2024. What changed since August to cause what I would describe as a significant double-digit percentage-wise revenue decline?

Brian Faith: Rick, that's the challenge with having large IP contract values. And when we're talking $3,000,000 type ASPs for these. So I think in the call, mentioned one clearly is in 2026. So that goes from this year into next year. And then some other smaller ones that contribute to that, but again, when you have $3,000,000 IP contracts, if they don't happen in the year the fiscal year, there's gonna be a big change in percentage-wise from the revenue levels that we're at today. Once that becomes more of the norm and we get more of these higher value contracts, like, we're talking about now, that starts to smooth out some of that lumpiness.

But when we're at the stage where we are now, there's almost unavoidable if something moves out that's gonna materially impact the percentage of that.

Rick Neaton: Okay. Thanks for that explanation. And thanks for having me on the call.

Brian Faith: Thanks, Rick. Of course.

Operator: This now concludes our question and answer session. I would like to turn the floor back over to Brian Faith for closing comments.

Brian Faith: Yeah. I want to thank everybody for joining us today. Hopefully, we'll connect with some of you at one of our upcoming events, including the Craig Hallum Alpha Select 101 Conference in New York on November 18, the semiconductor-focused annual New York summit also in New York on December 16, or the Annual Needham Growth Conference in early January 2026. Thank you, and have a good day.

Operator: Ladies and gentlemen, thank you for your participation. This does conclude today's teleconference. Please disconnect your lines, and have a wonderful day.

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